1. Field of the Invention
The present invention generally relates to dynamic latch-circuits and, more particularly, to a dynamic latch circuit design that utilizes power conservation techniques to minimize both set and restore power in the dynamic latch without sacrificing speed.
2. Background Description
Latch design often presents itself as one of the most significant development parameters in determining both system performance and power utilization. Latches of all kinds are abundantly used throughout designs and are absolutely essential in holding information to be processed and maintaining data integrity in the interim. For example, in microprocessor design, latches are an essential building block of fast memory storage devices called cache. One aspect of cache memory is latching (holding) control signals, such as an address line, that enter the cache. There are basically two types of latches, static latches and dynamic latches, the fastest of which being dynamic latches.
With increased system complexity and the introduction of additional parallel logic pipelines, particularly in reduced instruction set computer (RISC) architecture, the demand for latches is even greater and growing. With larger numbers and increasing utilization, the need for lower power latches is imperative.